Datasheet4U Logo Datasheet4U.com

PLS159A - Programmable logic sequencer 16 x 45 x 12

General Description

The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops.

These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC.

Key Features

  • 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (B). These yield variable I/O gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs. The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 4 inputs (I), bidirectional I/O lines (B), internal flip-flop outputs (Q), and Complement Array output (C). Th.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PLS153A Programmable logic arrays 18 × 42 × 10 Philips
PLS103 Field Programmable Gate Array Signetics
PLS1A151MDL4 CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS Nichicon
PLS1A271MDO1 CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS Nichicon
PLS1A471MDO1 CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS Nichicon

Other Datasheets by NXP Semiconductors

Part Number Description
PLS155 Programmable Logic Sequencer
PLS100 (PLS100 / PLS101) Programmable logic arrays
PLS101 (PLS100 / PLS101) Programmable logic arrays
PLS105 Field-Programmable Logic Sequencer
PLS167 FIELD PROGRAMMABLE LOGIC SEQUENCER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 45 × 12) PLS159A DESCRIPTION The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a “fold-back” inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (B). These yield variable I/O gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs. The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming I/O polarity and direction.