UJA1163 Datasheet - NXP

Mini high-speed CAN system

UJA1163 Features

* 2.1 General

* ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver

* Loop delay symmetry timing enables reliable communication at data rates up to 2 Mbit/s in the CAN FD fast phase

* Autonomous bus biasing according to ISO 11898-6

* Fully integrated 5 V/100 mA low-drop vo

UJA1163 General Description

The UJA1163 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a microcontroller. The UJA1163 can be operated in a very low-current Standby mode with bus wake-up capability and supports ISO 11898-6 complia.

UJA1163 Datasheet (253.47 KB)