NT5DS64M4BF
Features
CAS Latency and Frequency
CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166
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- - Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
- Differential clock inputs (CK and CK)
Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions mands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval SSTL_2 patible I/O interface VDDQ = 2.6V ± 0.1V VDD = 2.6V ± 0.1V Lead-free and Halogen-free product available
Description
The 256Mb DDR SDRAM is a...
