Dual JK Positive Edge-Triggered Flip-Flop
The ’F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to ’F74
data sheet) by connecting the J and K inputs.
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
n Guaranteed 4000V minimum ESD protection.
Ordering Code: See Section 0
74F109SC (Note 1)
54F109DM (Note 2)
74F109SJ (Note 1)
54F109FM (Note 2)
54F109LM (Note 2)
16-Lead (0.300" Wide) Molded Dual-in-Line
16-Lead Ceramic Dual-in-Line
16-Lead (0.150" Wide) Molded Small Outline,
16-Lead (0.300" Wide) Molded Small Outline,
16-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
FAST® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation DS009471
PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv Proof