Datasheet4U Logo Datasheet4U.com

74F109 - Dual JK Positive Edge-Triggered Flip-Flop

Download the 74F109 datasheet PDF. This datasheet also covers the 74F109PC variant, as both devices belong to the same dual jk positive edge-triggered flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops.

The clocking operation is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs.

Features

  • n Guaranteed 4000V minimum ESD protection. Ordering Code: See Section 0 Commercial Military 74F109PC 74F109SC (Note 1) 54F109DM (Note 2) 74F109SJ (Note 1) 54F109FM (Note 2) 54F109LM (Note 2) Package Number N16E J16A M16A M16D W16A E20A Package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74F109PC_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features n Guaranteed 4000V minimum ESD protection.
Datasheet originally released: |