74F109 Datasheet - National Semiconductor

Dual JK Positive Edge-Triggered Flip-Flop

74F109 General Description

The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous.

74F109 Datasheet (133.13 KB)

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74F109

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National Semiconductor

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133.13 KB

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Dual jk positive edge-triggered flip-flop.
54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Descript.

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74F109 Dual Positive Edge-Triggered Flip-Flop National Semiconductor

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74F109 General Description

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