Datasheet4U Logo Datasheet4U.com

CGS700V - Commercial Low Skew PLL 1 to 9 CMOS Clock Driver

Description

CGS700 is an off the shelf clock driver specifically designed around the PowerPc™ architecture.

It provides low skew outputs which are produced at different frequencies from three fixed input references.

Features

  • Guaranteed and tested: - 500 ps pin-to-pin skew (toSHL and toSLH) on 1X outputs.
  • Output buffer of nine drivers for large fanout.
  • 25 MHz-160 MHz output frequency range.
  • Outputs operating at 4X, 2X, 1X of the reference fre- quency for multi-frequency bus.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CGS702T400X5R High-Cap Screw Terminal Aluminum Electrolytic Capacitor CDE
CGS702U075R2L High-Cap Screw Terminal Aluminum Electrolytic Capacitor CDE
CGS703U016V4C High-Cap Screw Terminal Aluminum Electrolytic Capacitor CDE
CGS703U025X4C High-Cap Screw Terminal Aluminum Electrolytic Capacitor CDE
CGS703U035X4C High-Cap Screw Terminal Aluminum Electrolytic Capacitor CDE

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
CGS701ATV Commercial/ Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701AV Commercial/ Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701TV Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701V Low Skew PLL 1 to 8 CMOS Clock Driver
CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
>e.oo..n... ~National Q oC!J Semiconductor PRELIMINARY CGS700V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver General Description CGS700 is an off the shelf clock driver specifically designed around the PowerPc™ architecture. It provides low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz, 33 MHz or 40 MHz. The PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input. The device includes a TRI-STATE® control pin to disable the outputs while the PLL is still in lock.
Published: |