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CGS701TV - Low Skew PLL 1 to 8 CMOS Clock Driver

Download the CGS701TV datasheet PDF. This datasheet also covers the CGS701V variant, as both devices belong to the same low skew pll 1 to 8 cmos clock driver family and are provided as variant models within a single manufacturer datasheet.

General Description

CGS701 is an off the shelf clock driver specifically designed for today's high speed designs.

It provides low skew outputs which are produced at different frequencies from three fixed input references.

The XTALIN input pin is designed to be driven from a 15 MHz-50 MHz crystal oscillator.

Key Features

  • Guaranteed and tested: 500 ps pin-to-pin skew (tOSHL and tOSLH) on 1X out- puts. ± 500 ps propagation delay.
  • Output buffer of eight drivers for large fanout.
  • 25 MHz-160 MHz output frequency range.
  • Outputs operating at 4X, 2X, 1X of the reference frequency for multifrequency bus.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CGS701V-NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
CGS701ATV Commercial/ Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701AV Commercial/ Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701V Low Skew PLL 1 to 8 CMOS Clock Driver
CGS700V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
,.. o ~ o ~DNaStemiicoonnduactlor PRELIMINARY CGS701V Commercial/CGS701TV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver General Description CGS701 is an off the shelf clock driver specifically designed for today's high speed designs. It provides low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from a 15 MHz-50 MHz crystal oscillator. The PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input. The device includes a TRI-STATE® control pin to disable the outputs. This feature allows for low frequency functional testing and debugging.