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PRELIMINARY
CGS700V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
General Description
CGS700 is an off the shelf clock driver specifically designed around the PowerPc™ architecture. It provides low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz, 33 MHz or 40 MHz.
The PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input.
The device includes a TRI-STATE® control pin to disable the outputs while the PLL is still in lock.