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CGS702V - Commercial Low Skew PLL 1 to 9 CMOS Clock Driver

General Description

The CGS702 is an off-the-shelf clock driver specifically designed for today’s high speed processors It provides low skew outputs which are produced at different frequencies from three fixed input references The CGS702 is a reduced EMI version of the CGS700 The XTALIN input pin is designed to be driv

Key Features

  • Y Guaranteed and tested 500 ps pin-to-pin skew (TOSHL and TOSLH) on 1x outputs PentiumTM and PowerPCTM compatible Output buffer of nine drivers for large fanout 25 MHz.
  • 160 MHz output frequency range Outputs operating at 4x 2x 1x of the reference frequency for multi-frequency bus.

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Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
CGS700V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
CGS701ATV Commercial/ Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701AV Commercial/ Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701TV Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701V Low Skew PLL 1 to 8 CMOS Clock Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI September 1995 CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI General Description The CGS702 is an off-the-shelf clock driver specifically designed for today’s high speed processors It provides low skew outputs which are produced at different frequencies from three fixed input references The CGS702 is a reduced EMI version of the CGS700 The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz 33 MHz or 40 MHz The PLL using a charge pump and an internal loop filter multiplies this input frequency to create a maximum output frequency of four times the input The device includes a TRI-STATE control pin to disable the outputs while the PLL is st