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* 78MSPS Operation Low Power, 145mW/channel, 52 MHz, Dec=192 Tw.

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* Cellular Basestations Satellite Receivers Wireless Local Loop Receivers Digital Communications .

The CLC5903 block diagram is shown in Figure 2. The CLC5903 contains two identical digital down-conversion (DDC) circuits. Each DDC accepts an independently clocked 14-bit sample at up to 78MSPS, down converts from a selected carrier frequency to bas.

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