Datasheet4U Logo Datasheet4U.com

DS90CR283 - 28-Bit Channel Link

Datasheet Summary

Description

The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Features

  • n n n n n n n n n n n 66 MHz clock support Up to 231 Mbytes/s bandwidth Low power CMOS design ( < 610 mW) Power Down mode ( < 0.5 mW total) Up to 1.848 Gbit/s data throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS Standard Block Diagrams DS90CR283 DS90CR284 DS012889-27 DS012889-1 Order Number DS90CR283MTD See NS Package Number MT.

📥 Download Datasheet

Datasheet preview – DS90CR283

📁 Similar Datasheet

  • DS90CR285 - +3.3V Rising Edge Data Strobe LVDS (Texas Instruments)
  • DS90CR286 - +3.3V Rising Edge Data Strobe LVDS (Texas Instruments)
  • DS90CR286A - 3.3-V Rising Edge Data Strobe LVDS Receiver (Texas Instruments)
  • DS90CR286AT-Q1 - 3.3 V Rising Edge Data Strobe LVDS Receiver (Texas Instruments)
  • DS90CR287 - +3.3V Rising Edge Data Strobe LVDS (Texas Instruments)
  • DS90CR288A - +3.3V Rising Edge Data Strobe LVDS (Texas Instruments)
  • DS90CR215 - +3.3V Rising Edge Data Strobe LVDS (Texas Instruments)
  • DS90CR216 - +3.3V Rising Edge Data Strobe LVDS (Texas Instruments)
  • DS90CR216A - 3.3-V Rising Edge Data Strobe LVDS Receiver (Texas Instruments)
  • DS90CR216A-Q1 - 3.3-V Rising Edge Data Strobe LVDS Receiver (Texas Instruments)
Other Datasheets by National Semiconductor

Full PDF Text Transcription

Click to expand full text
DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz July 1997 DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz General Description The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR284 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction.
Published: |