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SCANSTA476 Datasheet

Eight Input IEEE 1149.1 Analog Voltage Monitor

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April 2005
SCANSTA476
Eight Input IEEE 1149.1 Analog Voltage Monitor
General Description
The SCANSTA476 is a low power, Analog Voltage Monitor
used for sampling or monitoring up to 8 analog/mixed-signal
input channels. Analog Voltage Monitors are valuable during
product development, environmental test, production, and
field service for verifying and monitoring power supply and
reference voltages. In a supervisory role, the ’STA476 is
useful for card or system-level health monitoring and prog-
nostics applications.
Instead of requiring an external microcontroller with a GPIO
interface, the ’STA476 features a common IEEE 1149.1
(JTAG) interface to select the analog input, initiate a mea-
surement, and access the results - further extending the
capabilities of an existing JTAG infrastructure.
The SCANSTA476 uses the VREF input as a reference. This
enables the SCANSTA476 to operate with a full-scale input
range of 0 to VDD, which can range from +2.7V to +5.5V.
The SCANSTA476 is packaged in a 16-lead non-pullback
LLP package that provides an extremely small footprint for
applications where space is a critical consideration. This
product operates over the industrial temperature range of
−40˚C to +85˚C.
Features
n Eight selectable Analog input channels
n Analog full-scale input range 0V to VDD
n Typical accuracy of 2 mV at maximum VDD
n Very low power operation
n Small package footprint in 16-lead, 5 x 5 x 0.8 mm LLP
n Single +2.7V to +5.5V supply operation
n IEEE 1149.1 (JTAG) compliant interface
Applications
n Measurement of Point Voltages
n Real-time Signal Monitoring
n System Health Monitoring and Prognostics
n Debug, Environmental Test, Production Test, Field
Service
n Supplement In-Circuit Tester (ICT) access
n Vital in Servers, Computing, Telecommunication and
Industrial equipment
n Essential in Medical, Data Storage, and Networking
equipment
Block Diagram
© 2005 National Semiconductor Corporation DS200835
20083521
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National Semiconductor Electronic Components Datasheet

SCANSTA476 Datasheet

Eight Input IEEE 1149.1 Analog Voltage Monitor

No Preview Available !

Connection Diagram
DAP = GND
(Top View)
20083522
Pin Descriptions
Pin No.
ANALOG I/O
16
15
14
13
12
11
10
9
2
Symbol
A0
A1
A2
A3
A4
A5
A6
A7
VREF
DIGITAL I/O
6
5
7
8
4
POWER SUPPLY
TDI
TDO
TMS
TCK
TRST
1,3 VDD
(Note 1)
GND
Description
Analog input 0. This signal can range from 0V to VREF.
Analog input 1. This signal can range from 0V to VREF.
Analog input 2. This signal can range from 0V to VREF.
Analog input 3. This signal can range from 0V to VREF.
Analog input 4. This signal can range from 0V to VREF.
Analog input 5. This signal can range from 0V to VREF.
Analog input 6. This signal can range from 0V to VREF.
Analog input 7. This signal can range from 0V to VREF.
Analog reference voltage input. VREF must be VDD. This pin should be connected to a quiet
+2.7V to +5.5V source (not directly to VDD) and bypassed to GND with 0.1 µF and 1 µF
monolithic capacitors located within 1 cm of the VREF pin.
Test Data Input to support IEEE 1149.1 features
Test Data Ouput to support IEEE 1149.1 features
Test Mode Select to support IEEE 1149.1 features
Test Clock to support IEEE 1149.1 features
Test Reset to support IEEE 1149.1 features
Positive supply pin. These pins should be connected to a quiet +2.7V to +5.5V source and
bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the
power pin.
Ground reference for CMOS circuitry. DAP is the exposed metal contact at the bottom of the
LLP package. The DAP is used as the primary GND connection to the device. It should be
connected to the ground plane with at least 4 vias for optimal low-noise and thermal
performance.
Note 1: Note that GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package.
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Part Number SCANSTA476
Description Eight Input IEEE 1149.1 Analog Voltage Monitor
Maker National Semiconductor
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SCANSTA476 Datasheet PDF






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