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MC10E155 Datasheet

5VECL 6-Bit 2:1 Mux-Latch

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MC10E155, MC100E155
5V ECL 6−Bit 2:1
Mux−Latch
Description
The MC10E/100E155 contains six 2:1 multiplexers followed by
transparent latches with singleended outputs. When both Latch
Enables (LEN1, LEN2) are LOW, the latch is transparent, and output
data is controlled by the multiplexer select control, SEL. A logic
HIGH on either LEN1 or LEN2 (or both) latches the outputs. The
Master Reset (MR) overrides all other controls to set the Q outputs
LOW.
The 100 Series contains temperature compensation.
Features
850 ps Max. LEN to Output
825 ps Max. D to Output
SingleEnded Outputs
Asynchronous Master Reset
Dual LatchEnables
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
PbFree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 239 Devices
PbFree Packages are Available*
http://onsemi.com
PLCC28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE155FNG
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 8
1
Publication Order Number:
MC10E155/D


  ON Semiconductor Electronic Components Datasheet  

MC10E155 Datasheet

5VECL 6-Bit 2:1 Mux-Latch

No Preview Available !

MC10E155, MC100E155
D5a D4b D4a D3b D3a NC VCCO
25 24 23 22 21 20 19
D5b 26
18 Q5
LEN1 27
17 Q4
LEN2 28
VEE
1
MR 2
Pinout: 28Lead PLCC
(Top View)
16 VCC
15 Q3
14 Q2
SEL 3
D0a 4
13 VCCO
12 Q1
5 6 7 8 9 10 11
D0b D1a D1b D2a D2b VCCO Q0
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 2. 28Lead Pinout
Table 1. PIN DESCRIPTION
PIN FUNCTION
D0a D04
D0b D4b
SEL
ECL Input Data a
ECL Input Data b
ECL Data Select Input
LEN1, LEN2
ECL Latch Enables
Q0 Q4
MR
ECL Outputs
Master Reset
VCC, VCCO
VEE
NC
Positive Supply
Negative Supply
No Connect
Table 2. TRUTH TABLE
SEL Data
Ha
Lb
D0a
D0b
MUX
SEL
Q
D
EN R
D1a
D1b
MUX
SEL
Q
D
EN R
D2a
D2b
MUX
SEL
Q
D
EN R
D3a
D3b
MUX
SEL
Q
D
EN R
D4a
D4b
MUX
SEL
DQ
EN
R
D5a
D5b
MUX
SEL
DQ
EN
R
SEL
LEN1
LEN2
MR
Figure 1. Logic Diagram
Q0
Q1
Q2
Q3
Q4
Q5
http://onsemi.com
2


Part Number MC10E155
Description 5VECL 6-Bit 2:1 Mux-Latch
Maker ON Semiconductor
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MC10E155 Datasheet PDF






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