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NB3M8302C Datasheet

3.3V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout Buffer

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NB3M8302C
3.3 V 200 MHz 1:2
LVCMOS/LVTTL Low Skew
Fanout Buffer
Description
The NB3M8302C is 1:2 fanout buffer with LVCMOS/LVTTL input
and output. The device supports the core supply voltage of 3.3 V (VDD
pin) and output supply voltage of 2.5 V or 3.3 V (VDDO pin). The
VDDO pin powers the two single ended LVCMOS/LVTTL outputs.
The NB3M8302C is Form, Fit and Function (pin to pin) compatible
to ICS8302 and ICS8302I. The NB3M8302C is qualified for industrial
operating temperature range.
Features
Input Clock Frequency up to 200 MHz
Low Output to Output Skew: 25 ps typical
Low Part to Part Skew: 250 ps typical
Low Additive RMS Phase Jitter
Input Clock Accepts LVCMOS/ LVTTL Levels
Operating Voltage:
Core Supply: VDD = 3.3 V ±5%
Output Supply: VDDO = 3.3 V ±5% or 2.5 V ±5%
Operating Temperature Range:
Industrial: −40°C to +85°C
These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
8302C
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 3
1
Publication Order Number:
NB3M8302C/D


  ON Semiconductor Electronic Components Datasheet  

NB3M8302C Datasheet

3.3V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout Buffer

No Preview Available !

NB3M8302C
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Number Name
1, 6 VDDO
2 VDD
3 CLK
4, 7 GND
5 Q1
8 Q0
Type
Output Power
Input and Core Power
LVCMOS/LVTTL Input
Ground
LVCMOS/LVTTL Output
LVCMOS/LVTTL Output
Description
Clock output Supply pin.
Input and Core Supply pin.
Clock Input. Internally pull−down.
Supply Ground.
LVCMOS/LVTTL Clock output.
LVCMOS/LVTTL Clock output.
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition
Min Max Unit
VDD, VDDO
VI
Tstg
qJA
Power Supply
Input Voltage
Storage Temperature
Thermal Resistance (Junction to Ambient)
SOIC−8
0 lfpm
500 lfpm
− 4.6 V
−0.5 VDD + 0.5 V V
−65
+150
_C
_C/W
80
55
qJC Thermal Resistance (Junction to Case)
(Note 1)
12−17
_C/W
Tsol
MSL
Wave Solder
Moisture Sensitivity
SOIC−8
3 sec
265 _C
Indefinite Time Out of Drypack
(Note 2)
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power)
2. For additional information, see Application Note AND8003/D.
www.onsemi.com
2


Part Number NB3M8302C
Description 3.3V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout Buffer
Maker ON Semiconductor
Total Page 6 Pages
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