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NB3N853531E Datasheet

3.3V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer

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NB3N853531E
3.3 V Xtal or
LVTTL/LVCMOS Input 2:1
MUX to 1:4 LVPECL Fanout
Buffer
Description
The NB3N853531E is a low skew 3.3 V supply 1:4 clock
distribution fanout buffer. An input MUX selects either a
Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by
using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with
LVCMOS / LVTTL levels.
The single ended CLK input is translated to four LVPECL Outputs.
Using the crystal input, the NB3N853531E can be a Clock Generator.
A CLK_EN pin can enable or disable the outputs synchronously to
eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable
outputs, LOW to disable outputs).
Features
Four Differential 3.3 V LVPECL Outputs
Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Max)
Device to Device Skew 200 ps (Max)
Propagation Delay 1.8 ns (Max)
Operating Range: VCC = 3.3 ±5% V( 3.135 to 3.465 V)
Additive Phase Jitter, RMS: 0.053 ps (Typ)
Synchronous Clock Enable Control
Industrial Temp. Range (40°C to 85°C)
PbFree TSSOP20 Package
Ambient Operating Temperature Range 40°C to +85°C
These are PbFree Devices
http://onsemi.com
MARKING
DIAGRAM
TSSOP20
DT SUFFIX
CASE 948E
NB3N
531E
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 7 of this data sheet.
CLK_EN
Pullup
CLK
Pulldown
XTAL_IN
XTAL_OUT
OSC
CLK_SEL
Pulldown
0
1
D
Q
Figure 1. Simplified Logic Diagram
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
© Semiconductor Components Industries, LLC, 2012
March, 2012 Rev. 6
1
Publication Order Number:
NB3N853531E/D


  ON Semiconductor Electronic Components Datasheet  

NB3N853531E Datasheet

3.3V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer

No Preview Available !

NB3N853531E
VEE
CLK_EN
CLK_SEL
CLK
nc
XTAL_IN
XTAL_OUT
nc
nc
VCC
1
2
3
4
5
6
7
8
9
10
20 Q0
19 Q0
18 VCC
17 Q1
16 Q1
15 Q2
14 Q2
13 VCC
12 Q3
11 Q3
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5, 8, 9
6
7
10, 13, 18
11, 14, 16,
19
12, 15, 17,
20
Name
VEE
CLK_EN
CLK_SEL
CLK
nc
XTAL_IN
XTAL_OUT
VCC
Q[3:0]
Q[3:0]
I/O
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVCMOS /
LVTTL
Crystal
Crystal
LVPECL
LVPECL
Open De-
fault
Pullup
Pulldown
Description
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects crystal, LOW selects CLK input)
Pulldown Clock Input. Float open when unused.
No Connect
Crystal Oscillator Input (used with pin 7). Float open when unused.
Crystal Oscillator Output (used with pin 6). Float open when unused.
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Outputs (See AND8020 for termination)
True Differential Outputs (See AND8020 for termination)
Table 2. FUNCTIONS
Inputs
Outputs
CLK_EN
CLK_SEL
Input Function
Output Function
Qx Qx
00
CLK input selected
Disabled
LOW
HIGH
0 1 Crystal Inputs Selected
Disabled
LOW
HIGH
10
CLK input selected
Enabled
CLK0
Invert of
CLK1
1 1 Crystal Inputs Selected
Enabled
CLK1
Invert of
CLK1
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
http://onsemi.com
2


Part Number NB3N853531E
Description 3.3V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer
Maker ON Semiconductor
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