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  ON Semiconductor Electronic Components Datasheet  

NB4N11M Datasheet

Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator

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NB4N11M pdf
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NB4N11M
3.3 V 2.5 Gb/s Multi Level
Clock/Data Input to CML
Receiver/ Buffer/ Translator
Description
The NB4N11M is a differential 1to2 clock/data
distribution/translation chip with CML output structure, targeted for
highspeed clock/data applications. The device is functionally
equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device
produces two identical differential output copies of clock or
data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,
NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and
other clock/data distribution applications.
Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS
(See Table 5). The CML outputs are 16 mA open collector
(See Figure 18) which requires resistor (RL) load path to VTT
termination voltage. The open collector CML outputs must be
terminated to VTT at power up. Differential outputs produces
current–mode logic (CML) compatible levels when receiver loaded
with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies
(see Figure 19). This simplifies device interface by eliminating a need
for coupling capacitors.
The device is offered in a small 8pin TSSOP package.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
Maximum Input Clock Frequency > 2.5 GHz
Maximum Input Data Rate > 2.5 Gb/s
Typically 1 ps of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 W
420 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and
VTT = 1.8 V to 3.6 V
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
These are PbFree Devices*
http://onsemi.com
8
1
TSSOP8
DT SUFFIX
CASE 948R
MARKING
DIAGRAM*
8
E11M
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
D
D
Q1
Q1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
November, 2005 Rev. 1
1
Publication Order Number:
NB4N11M/D


  ON Semiconductor Electronic Components Datasheet  

NB4N11M Datasheet

Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator

No Preview Available !

NB4N11M pdf
Q0 1
Q0 2
NB4N11M
8 VCC
7D
Q1 3
6D
Q1 4
5 VEE
Figure 2. Pinout (Top View) and Logic Diagram
Table 1. Pin Description
Pin Name
1 Q0
I/O
CML Output
2 Q0
3 Q1
CML Output
CML Output
4 Q1
CML Output
5 VEE
6D
LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
7D
LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
8 VCC
Description
Noninverted differential output. Typically receiver terminated with 50 W
resistor to VTT. Open collector CML outputs must be terminated to VTT at
powerup.
Inverted differential output. Typically receiver terminated with 50 W resistor
to VTT. Open collector CML outputs must be terminated to VTT at powerup.
Noninverted differential output. Typically receiver terminated with 50 W
resistor to VTT. Open collector CML outputs must be terminated to VTT at
powerup.
Inverted differential output. Typically receiver terminated with 50 W resistor
to VTT. Open collector CML outputs must be terminated to VTT at powerup.
Negative supply voltage.
Inverted differential input.
Noninverted differential input.
Positive supply voltage.
http://onsemi.com
2


Part Number NB4N11M
Description Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator
Maker ON Semiconductor
Total Page 11 Pages
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