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  ON Semiconductor Electronic Components Datasheet  

NB4N11S Datasheet

3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator

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NB4N11S
3.3 V 1:2 AnyLevelInput
to LVDS Fanout Buffer /
Translator
The NB4N11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevelTM input signals: LVPECL, CML, LVCMOS,
LVTTL, or LVDS. These signals will be translated to LVDS and two
identical copies of Clock or Data will be distributed, operating up to
2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N11S is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock or Data
distribution applications.
The NB4N11S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB4N11S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB4N11S is functionally equivalent to the EP11, LVEP11,
SG11 or 7L11M devices and is offered in a small 3 mm X 3 mm
16−QFN package. Application notes, models, and support
documentation are available at www.onsemi.com.
Features
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
Device DDJ = 10 ps
www.DataSheet4U.com
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB4N
11S
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTD Q0
D
D
VTD
Figure 1. Logic Diagram
Q1
Q1
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 0
1
Publication Order Number:
NB4N11S/D


  ON Semiconductor Electronic Components Datasheet  

NB4N11S Datasheet

3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator

No Preview Available !

NB4N11S
VCC VCC VCC VCC
16 15 14 13
Exposed Pad (EP)
Q0 1
Q0 2
Q1 3
Q1 4
NB4N11S
12 VTD
11 D
10 D
9 VTD
5 678
VCC NC VEE VEE
Figure 3. NB4N11S Pinout, 16−pin QFN (Top View)
www.DataSheet4U.com
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1 Q0
LVDS Output
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q0
LVDS Output
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3 Q1
LVDS Output
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q1
LVDS Output
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 VCC
6 NC
− Positive Supply Voltage.
No Connect.
7 VEE
Negative Supply Voltage.
8 VEE
Negative Supply Voltage.
9 VTD
− Internal 50 W termination pin for D.
10
D
LVPECL, CML, LVDS,
Inverted Differential Clock/Data Input (Note 1).
LVCMOS, LVTTL
11
D
LVPECL, CML, LVDS,
Non−inverted Differential Clock/Data Input (Note 1).
LVCMOS, LVTTL
12 VTD
− Internal 50 W termination pin for D.
13 VCC
− Positive Supply Voltage.
14 VCC
− Positive Supply Voltage.
15 VCC
− Positive Supply Voltage.
16 VCC
− Positive Supply Voltage.
EP Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heat−sinking conduit. The exposed pad may only be
electrically connected to VEE.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
http://onsemi.com
2


Part Number NB4N11S
Description 3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator
Maker ON Semiconductor
Total Page 10 Pages
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