3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single−ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
Output drive current at IREF (Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect IREF to VCC. See
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
• Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each
• Additive Phase RMS Jitter: 1 ps Max
• Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• Differential HCSL Output Level (700 mV Peak−to−Peak)
• Pb−Free Packages are Available
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Pin Configuration (Top View)
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 6
Publication Order Number: