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  ON Semiconductor Electronic Components Datasheet  

NB4N121K Datasheet

3.3V Differential 1:21 Differential Fanout Clock Driver

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NB4N121K
3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Singleended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors.
Output drive current at IREF (Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect IREF to VCC. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
Additive Phase RMS Jitter: 1 ps Max
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Differential HCSL Output Level (700 mV PeaktoPeak)
PbFree Packages are Available
http://onsemi.com
1 52
QFN52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB4N
121K
AWLYYWWG
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
Q1
CLK
CLK
Q19
VTCLK
VCC
GND
RREF
Q19
Q20
IREF Q20
Figure 1. Pin Configuration (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 6
1
Publication Order Number:
NB4N121K/D


  ON Semiconductor Electronic Components Datasheet  

NB4N121K Datasheet

3.3V Differential 1:21 Differential Fanout Clock Driver

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IREF 1
GND 2
VTCLK 3
CLK 4
CLK 5
VTCLK 6
VCC 7
Q20 8
Q20 9
Q19 10
Q19 11
Q18 12
Q18 13
NB4N121K
NB4N121K
Exposed Pad (EP)
39 VCC
38 Q6
37 Q6
36 Q7
35 Q7
34 Q8
33 Q8
32 Q9
31 Q9
30 Q10
29 Q10
28 Q11
27 Q11
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IREF
Output
Output current programming pin to select load drive. For 1X
configuration, connect IREF to GND, or for 2X configuration, connect
IREF to VCC (See Figure 9).
2
GND
Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
3, 6
VTCLK,
Internal 50 W Termination Resistor connection Pins. In the differential
VTCLK
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to selfoscillation.
4 CLK LVPECL Input CLOCK Input (TRUE)
5 CLK LVPECL Input CLOCK Input (INVERT)
7, 26, 39, 52
VCC Positive Supply pins. VCC pins must be externally connected to a power
supply to guarantee proper operation.
8, 10, 12, 14, 16, 18, 20, 22,
24, 27, 29, 31, 33, 35, 37, 40,
42, 44, 46, 48, 50
Q[200] HCSL Output Output (INVERT)
9, 11, 13, 15, 17, 19, 21, 23,
25, 28, 30, 32, 34, 36, 38, 41,
43, 45, 47, 49, 51
Q[200] HCSL Output Output (TRUE)
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heatsinking conduit for
proper thermal operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
http://onsemi.com
2


Part Number NB4N121K
Description 3.3V Differential 1:21 Differential Fanout Clock Driver
Maker ON Semiconductor
Total Page 9 Pages
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