an input threshold hysteresis of approximately 25 mV, providing increased noise immunity and stability. The device is offered in a small 8−pin TSSOP package (MSOP−8 compa.

The CML outputs are 16 mA open collector (see Figure 18) which requires resistor (RL) load path to VTT termination volt.

Pin Name I/O Description 1 NC − No Connect. 2 D ECL, CML, LVCMOS, LVDS, Noninverted Differential Input. (Note 1) LVTTL Input 3 D ECL, CML, LVCMOS, LVDS, Inverted Differential Input. (Note 1) LVTTL Input 4 VBB − Internally Generate.

NB4N111K

NB4N1158

NB4N11M

NB4N11S

NB4N121K

NB4N441

NB4N507A

NB4N527S

NB4N7132

NB4N840M

NB4N855S

NB4148

NB4L16M