PI6CV855 memory equivalent, pll clock driver for 2.5v sstl 2 ddr sdram memory.
PLL clock distribution optimized for SSTL_2 DDR SDRAM applications. Distributes one differential clock input pair to five differential clock output pairs. Inputs (C.
Distributes one differential clock input pair to five differential clock output pairs. Inputs (CLK,CLK) and (FBIN,F.
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