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PLL205-14 - Programmable Clock Generator

Datasheet Summary

Description

Name VDD1 VDD2 VDD3 VDD4 VDDL1 VDDL2 GND XIN XOUT PD# PCI_STOP/ WDRESET# CPU_STOP AGP_STOP REF_STOP PCI(0:8) Number 1 5 15,23 25 40 33 2,8,12,19,29, 32,37,43 3 4 34 35 36 44 45 10,11,13,14, 16,17,18,20,21 Type P P P P P P P I O I B I I I O Description Power supply for REF(0:1), REF_F and crystal

Features

  • PIN.

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Datasheet preview – PLL205-14

Datasheet Details

Part number PLL205-14
Manufacturer PhaseLink
File Size 286.16 KB
Description Programmable Clock Generator
Datasheet download datasheet PLL205-14 Datasheet
Additional preview pages of the PLL205-14 datasheet.

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Full PDF Text Transcription

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m Preliminary PLL205-14 o c . Programmable Clock Generator for VIA KT-266 Chipset U 4 t FEATURES PIN CONFIGURATION e e frequencies for VIA KT266 • Generates all clock h chipset. S a • Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and 10 PCI. D . • w Enhanced PCI Output Drive selectable by I2C. •w One 48MHz clock and 24_48MHz clock via I2C. w• Three 14.318MHz reference clocks. • • • • • • • Power management control to stop CPU, PCI, REF, 24_48MHz, 48MHz and AGP clocks. Supports 2-wire I2C serial bus interface with readback. Single byte micro-step linear Frequency Programming via I2C with glitch free smooth switching. Built-in programmable watchdog timer up to 63 seconds with 1-second interval.
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