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PLL130-09 - High Speed Translator Buffer to LVDS

Datasheet Summary

Description

The PLL130-09 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz.

It provides a pair of differential LVDS output.

Any input signal with at least 100mV swing can be used as reference signal.

Features

  • Differential LVDS output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN.

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Datasheet preview – PLL130-09

Datasheet Details

Part number PLL130-09
Manufacturer PhaseLink Corporation
File Size 269.84 KB
Description High Speed Translator Buffer to LVDS
Datasheet download datasheet PLL130-09 Datasheet
Additional preview pages of the PLL130-09 datasheet.

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Full PDF Text Transcription

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PLL130-09 High Speed Translator Buffer to LVDS FEATURES • • • • • Differential LVDS output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) GND REF_IN 1 2 3 4 VDD 8 7 6 5 GND VDD GND LVDS_BAR VDD PLL130-09 www.DataSheet4U.com DESCRIPTION The PLL130-09 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz. It provides a pair of differential LVDS output. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, CMOS, or PECL to LVDS.
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