HYB25DC256163CE-5, HYB25DC256163CE-4 - 256-Mbit Double-Data-Rate SGRAM

Qimonda

Datasheet Details

Part number	HYB25DC256163CE-5, HYB25DC256163CE-4
Manufacturer	Qimonda
File Size	677.92 KB
Description	256-Mbit Double-Data-Rate SGRAM
Datasheet	HYB25DC256163CE-4-Qimonda.pdf
Note	This datasheet PDF includes multiple part numbers: HYB25DC256163CE-5, HYB25DC256163CE-4. Please refer to the document for exact specifications by model.

The 256-Mbit Double-Data-Rate SGRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.

of the product family HYB25DC256163CE and the ordering information. 1.1 Features.
Double data rate architecture: two data transfers per clock cycle.
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for reads and is center-aligned with data for writes.
Differential clock inputs (CK and CK).
Four internal banks for concurrent operation.
Data mask.

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Published: Sep 28, 2015 |