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8531-01 - Differential-to3.3V LVPECL Fanout Buffer

General Description

The 8531-01 is a low skew, high performance 1 - t o - 9 D i f fe r e n t i a l - t o - 3 .

3 V LV P E C L Fa n o u t Buffer and a member of the family of High Pe r fo r m a n c e C l o ck S o l u t i o n s f r o m I D T.

T h e 8531-01 has two selectable clock inputs.

Key Features

  • Nine differential 3.3V LVPECL outputs.
  • Selectable differential CLK, nCLK or LVPECL clock inputs.
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL.
  • Maximum output frequency: 500MHz.
  • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input.
  • Additive phase jitt.

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Datasheet Details

Part number 8531-01
Manufacturer Renesas
File Size 377.02 KB
Description Differential-to3.3V LVPECL Fanout Buffer
Datasheet download datasheet 8531-01 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Low Skew, 1-to-9, Differential-to3.3V LVPECL Fanout Buffer 8531-01 Data Sheet GENERAL DESCRIPTION The 8531-01 is a low skew, high performance 1 - t o - 9 D i f fe r e n t i a l - t o - 3 . 3 V LV P E C L Fa n o u t Buffer and a member of the family of High Pe r fo r m a n c e C l o ck S o l u t i o n s f r o m I D T. T h e 8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew characteristics make the 8531-01 ideal for high performance workstation and server applications.