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85310I-11 Datasheet

2.5V LVPECL/ECL Fanout Buffer

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Low Skew, 1-to-10 Differential-to-3.3V,
2.5V LVPECL/ECL Fanout Buffer
85310I-11
DATA SHEET
General Description
The 85310I-11 is a low skew, high performance 1-to-10
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer. The CLKx,
nCLKx pairs can accept most standard differential input levels. The
85310I-11 is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the 85310I-11 ideal for those clock distribution
applications demanding well defined performance and repeatability.
Features
Ten differential 2.5V, 3.3V LVPECL/ECL output pair
Two selectable differential input pairs
Differential CLKx, nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 700MHz
Translates any single ended input signal to 3.3V LVPECL levels
with resistor bias on nCLK input
Output skew: 30ps (typical)
Part-to-part skew: 140ps (typical)
Propagation delay: 2ns (typical)
Additive phase jitter, RMS: <0.13ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free RoHS compliant package
Block Diagram
CLK0 Pulldown
nCLK0 Pullup
CLK1 Pulldown
nCLK1 Pullup
0
1
CLK_SEL Pulldown
CLK_EN Pullup D
LE
Q
85310I-11 Rev F 7/8/15
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Pin Assignment
VCC
CLK_SEL
CLK0
nCLK0
CLK_EN
CLK1
nCLK1
VEE
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
85310I-11
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
1 ©2015 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

85310I-11 Datasheet

2.5V LVPECL/ECL Fanout Buffer

No Preview Available !

85310I-11 DATA SHEET
Table 1. Pin Descriptions
Number
1
2
3
4
5
Name
VCC
CLK_SEL
CLK0
nCLK0
CLK_EN
Type
Power
Input
Pulldown
Input
Input
Pulldown
Pullup
Input
Pullup
Description
Positive supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
6
CLK1
Input
Pulldown Non-inverting differential clock input.
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
nCLK1
VEE
VCCO
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Inverting differential clock input.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
2
Rev F 7/8/15


Part Number 85310I-11
Description 2.5V LVPECL/ECL Fanout Buffer
Maker Renesas
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