8SLVD1204 Datasheet - Renesas

LVDS Output Fanout Buffer

8SLVD1204 Features

* Four low skew, low additive jitter LVDS output pairs

* Two selectable differential clock input pairs

* Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL

* Maximum input clock frequency: 2GHz

* LVCMOS/LVTTL interf

8SLVD1204 General Description

The 8SLVD1204 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1204 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew ch.

8SLVD1204 Datasheet (768.08 KB)