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ICS8546-01 Datasheet

Crystal-to-LVDS Fanout Buffer

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Low Skew, 1-to-6, Crystal-to-LVDS
Fanout Buffer
ICS8546-01
General Description
The ICS8546-01 is a low skew, high performance 1-to-6 Crystal
Oscillator-to-LVDS Fanout Buffer. The ICS8546-01 has selectable
crystal, single ended or differential clock inputs. The single-ended
clock input accepts LVCMOS or LVTTL input levels and translate
them to LVDS levels. The CLK1, nCLK1 pair can accept most
standard differential input levels. The output enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8546-01 ideal for those applications demanding well defined
performance and repeatability.
DATA SHEET
Features
Six 3.3V or 2.5V LVDS outputs
Selectable crystal oscillator, differential CLK1, nCLK1 pair
or LVCMOS/LVTTL clock input
CLK1, nCLK1 pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL
Maximum output frequency: 266MHz
Crystal frequency range: 14MHz - 40MHz
Output skew: 55ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 2.45ns (maximum)
Full 3.3V or 2.5V supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
XTAL_IN
XTAL_OUT
OSC
00
CLK0 Pulldown
01
CLK1 Pulldown
1X
nCLK1
Pullup
D
Q
LE
Q0
nQ0
6 LVDS Outputs
Q5
nQ5
Pin Assignment
nQ2 1
Q2 2
VDDO 3
nQ1 4
Q1 5
GND 6
nQ0 7
Q0 8
CLK_SEL0 9
XTAL_IN 10
XTAL_OUT 11
CLK_EN 12
24 Q3
23 nQ3
22 VDDO
21 Q4
20 nQ4
19 VDD
18 Q5
17 nQ5
16 CLK_SEL1
15 nCLK1
14 CLK1
13 CLK0
ICS8546-01
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
1
©2011 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

ICS8546-01 Datasheet

Crystal-to-LVDS Fanout Buffer

No Preview Available !

ICS8546-01 Data Sheet
LOW SKEW, 1-TO 6, CRYSTAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
Name
nQ2, Q2
Type
Output
Description
Differential output pair. LVDS interface levels.
3, 22
4, 5
6
7, 8
9,
16
10,
11
12
13
14
15
17, 18
19
20, 21
23, 24
VDDO
nQ1, Q1
GND
nQ0, Q0
CLK_SEL0,
CLK_SEL1
XTAL_IN,
XTAL_OUT
CLK_EN
CLK0
CLK1
nCLK1
nQ5, Q5
VDD
nQ4, Q4
nQ3, Q3
Power
Output
Power
Output
Input
Input
Input
Input
Input
Input
Output
Power
Output
Output
Output supply pins.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Pulldown Clock select pins. LVCMOS/LVTTL interface levels.
Pullup
Pulldown
Pulldown
Pullup
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When
LOW, the outputs are disabled. LVCMOS / LVTTL interface levels. See Table 3.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. LVDS interface levels.
Positive supply pin.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8546AG-01 REVISION A FEBRUARY 25, 2011
2
©2011 Integrated Device Technology, Inc.



Part Number ICS8546-01
Description Crystal-to-LVDS Fanout Buffer
Maker Renesas
Total Page 3 Pages
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ICS8546-01 Datasheet PDF





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