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ICS854S202I-01 Datasheet

Differential-To-LVDS Multiplexer

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12:2, Differential-To-LVDS Multiplexer
ICS854S202I-01
DATASHEET
General Description
The ICS854S202I-01 is a 12:2 Differential-to-LVDS Clock Multiplexer
which can operate up to 3GHz. The ICS854S202I-01 has twelve se-
lectable differential clock inputs, any of which can be independently
routed to either of the two LVDS outputs. The CLKx, nCLKx input
pairs can accept LVPECL, LVDS or CML levels. The fully differential
architecture and low propagation delay make it ideal for use in clock
distribution circuits.
Features
• Two differential 2.5V LVDS clock outputs
• Twelve selectable differential clock inputs
• CLKx, nCLKx pairs can accept the following differential input levels:
LVPECL, LVDS, CML
• Maximum output frequency: 3GHz
• Propagation delay: 1.1ns (maximum)
• Input skew: 100ps (maximum)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS (12kHz – 20MHz): 0.16ps (typical)
• Full 2.5V operating supply mode
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
SELA_[3:0] Pulldown
4
CLK0 Pulldown
nCLK0 Pullup/Pulldown
CLK1 Pulldown
nCLK1 Pullup/Pulldown
CLK2 Pulldown
nCLK2 Pullup/Pulldown
CLK3 Pulldown
nCLK3 Pullup/Pulldown
CLK4 Pulldown
nCLK4 Pullup/Pulldown
CLK5 Pulldown
nCLK5 Pullup/Pulldown
CLK6 Pulldown
nCLK6 Pullup/Pulldown
CLK7 Pulldown
nCLK7 Pullup/Pulldown
CLK8 Pulldown
nCLK8 Pullup/Pulldown
CLK9 Pulldown
nCLK9 Pullup/Pulldown
CLK10 Pulldown
nCLK10 Pullup/Pulldown
CLK11 Pulldown
nCLK11 Pullup/Pulldown
SELB_[3:0] Pulldown
4
QA
nQA
Pullup OEA
CLK2
nCLK2
SELA_0
SELA_1
VDD
QA
nQA
GND
SELA_2
SELA_3
CLK3
nCLK3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
4
ICS854S202I-01
34
33
5
48-Pin LQFP
32
6 7mm x 7mm x 1.4mm 31
7
package body
30
8
Y Package
29
9
10
Top View
28
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
CLK9
nCLK9
SELB_0
SELB_1
VDD
QB
nQB
GND
SELB_2
SELB_3
CLK8
nCLK8
QB
nQB
Pullup OEB
ICS854S202AYI-01 REV. A DECEMBER 18, 2012
1
©2012 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

ICS854S202I-01 Datasheet

Differential-To-LVDS Multiplexer

No Preview Available !

ICS854S202I-01 Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3,
4,
9,
10
5, 18, 32, 43
6, 7
8, 15, 22, 29,
39, 46
11
12
13
14
16
17
18, 43
19
20
21
23
24
25
26
27,
28,
33,
34
30, 31
35
36
37
38
40
41
42
44
Name
CLK2
nCLK2
SELA_0,
SELA_1,
SELA_2,
SELA_3
VDD
QA, nQA
GND
CLK3
nCLK3
nCLK4
CLK4
nCLK5
CLK5
VDD
OEA
CLK6
nCLK6
CLK7
nCLK7
nCLK8
CLK8
SELB_3,
SELB_2,
SELB_1,
SELB_0
nQB, QB
nCLK9
CLK9
nCLK10
CLK10
nCLK11
CLK11
OEB
CLK0
Input
Input
Input
Type
Pulldown
Pullup/Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Clock select pins for Bank A output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3B.
Power
Output
Power
Input
Input
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Power supply pins.
Clock outputs. LVDS interface levels.
Power supply ground.
Pulldown
Pullup/Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Positive supply pins.
Output enable pin. Controls enabling and disabling of QA, nQA
output pair. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Input
Pulldown
Clock select pins for Bank B output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3C.
Output
Input
Input
Input
Input
Input
Input
Input
Input
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup
Pulldown
Clock outputs. LVDS interface levels.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Output enable pin. Controls enabling and disabling of QB, nQB
output pair. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
ICS854S202AYI-01 REV. A DECEMBER 18, 2012
2
©2012 Integrated Device Technology, Inc.



Part Number ICS854S202I-01
Description Differential-To-LVDS Multiplexer
Maker Renesas
Total Page 3 Pages
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