* Low skew, low jitter PLL clock driver
* 1 to 10 differential clock distribution (SSTL_2)
* Feedback pin for input to output synchronization
* PD# for power management
* Spread Spectrum tolerant inputs Switching Characteristics:
* CYCLE - CYCLE jitte
ICS95V157 Datasheet (352.87 KB)
ICS95V157
352.87 KB
2.5v single-ended to sstl_2 clock driver.
ICS95V1 5 7 2.5V Single-Ended to SSTL_2 Clock Driver (45MHz - 233MHz) Recommended Application: Single-ended clock input with zero delay board fan ou.
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