IDT5V41067A
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
Pin Assignment
^SEL 1
VDDIN 2
DIF_IN1 3
DIF_IN1# 4
^PD# 5
DIF_IN2 6
DIF_IN2# 7
^OE 8
GND 9
IR EF 10
20 DIF_0
19 DIF_0#
18 DIF_1
17 DIF_1#
16 GND
15 VDD
14 DIF_2
13 DIF_2#
12 DIF_3
11 DIF_3#
Note: Pins preceeded by '*^ have internal
120K ohm pull up resistors
20-pin (173mil) TSSOP
Select Table
SEL
0
1
Outputs
DIF_IN2
DIF_IN1
Pin Descriptions
PIN #
PIN NAME
1 ^SEL
2 VDDIN
3 DIF_IN1
4 DIF_IN1#
PIN TYPE
DESCRIPTION
IN Selects between one of two inputs . This pin has internal pull up resis tor.
PWR Power pin for the Inputs, nominal 3.3V
IN 0.7 V Differential TRUE input
IN 0.7 V Differential Complementary Input
5 ^PD#
Asynchronous active low input pin used to power down the device. The internal
IN
c locks are dis abled and the VCO and the crystal os c. (if any) are stopped.
6 DIF_IN2
7 DIF_IN2#
IN 0.7 V Differential TRUE input
IN 0.7 V Differential Complementary Input
8 ^OE
Activ e high input for enabling outputs. This pin has an internal pull up resistor.
IN
0 = disable outputs, 1= enable outputs
9 GND
10 IREF
11 DIF_3#
12 DIF_3
13 DIF_2#
14 DIF_2
15 VDD
16 GND
17 DIF_1#
18 DIF_1
19 DIF_0#
20 DIF_0
PWR
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
Ground pin.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the s tandard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
IDT® 2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
2
IDT5V41067A
REV F 112211
