PSD813F1A
FEATURES
SUMMARY
- DUAL BANK FLASH MEMORIES
Figure 1. Packages
- 1 Mbit of Primary Flash Memory (8
Uniform Sectors)
)- 256 Kbit Secondary EEPROM (4 Uniform t(s Sectors)
- Concurrent operation: read from one ucmemory while erasing and writing the dother ro )- 16 Kbit SRAM P t(s- PLD WITH MACROCELLS te c- Over 3,000 Gates Of PLD: DPLD and le u CPLD d- DPLD
- User-defined Internal chip-select so rodecoding b P- CPLD with 16 Output Macrocells (OMCs)
- O teand 24 Input Macrocells (IMCs)
- 27 RECONFIGURABLE I/Os
) le- 27 individually configurable I/O port pins t(s sothat can be used for the following c bfunctions (16 I/O ports configurable as uopen-drain outputs): d
- OMCU I/Os ro )PLD I/Os P t(s Latched MCU address output; and te c Special function I/Os le u- ENHANCED JTAG SERIAL PORT so rod- Built-in JTAG-pliant serial port allows full-chip In-System Programmability (ISP) b P- Efficient manufacturing allows for easy O teproduct testing and programming le- PAGE REGISTER o- Internal page...
