Datasheet Summary
Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V
NOT FOR NEW DESIGN
Features
SUMMARY
- DUAL BANK FLASH MEMORIES
Figure 1. Packages
- 1 Mbit of Primary Flash Memory (8
Uniform Sectors)
)- 256 Kbit Secondary EEPROM (4 Uniform t(sSectors)
- Concurrent operation: read from one ucmemory while erasing and writing the dother ro )- 16 Kbit SRAM P t(s- PLD WITH MACROCELLS te c- Over 3,000 Gates Of PLD: DPLD and le uCPLD d- DPLD
- User-defined Internal chip-select so rodecoding b P- CPLD with 16 Output Macrocells (OMCs)
- O teand 24 Input Macrocells (IMCs)
- 27 RECONFIGURABLE I/Os
) le- 27 individually configurable I/O port pins t(s sothat can be used for the...