PSD813F2V Overview
10 PSD ARCHITECTURAL OVERVIEW.
PSD813F2V Key Features
- FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUS
- DUAL BANK FLASH MEMORIES
- UP TO 2 Mbit OF PRIMARY FLASH MEMORY (8 Uniform Sectors, 32K x8)
- UP TO 256 Kbit SECONDARY FLASH
- Concurrent operation: READ from one
- UP TO 256 Kbit of SRAM
- user defined internal chip select bdecoding
- HIGH ENDURANCE
- 100,000 Erase/WRITE Cycles of Flash Memory
- 1,000 Erase/WRITE Cycles of PLD