K3S7V2000M-TC - 64M-Bit (4Mx16 /2Mx32) Synchronous MASK ROM

Description

The K3S7V2000M-TC is a synchronous high bandwidth mask programmable ROM fabricated with SAMSUNG′s high performance CMOS process technology and is organized either as 4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double word mode) depending on polarity of WORD pin.(see pin function description).

Features

JEDEC standard 3.3V power supply.
LVTTL compatible with multiplexed address.
Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16).
Switchable organization 4,194,304 x 16(word mode) / 2,097,152 x 32(double word mode).
All inputs are sampled at the rising edge of the system clock.
Read Performance at memory point of view @33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3) @50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4) @66.

Samsung

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Datasheet Details

Part number	K3S7V2000M-TC
Manufacturer	Samsung
File Size	1.06 MB
Description	64M-Bit (4Mx16 /2Mx32) Synchronous MASK ROM
Datasheet	K3S7V2000M-TC Datasheet
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K3S7V2000M-TC 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16) • Switchable organization 4,194,304 x 16(word mode) / 2,097,152 x 32(double word mode) • All inputs are sampled at the rising edge of the system clock • Read Performance at memory point of view @33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3) @50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4) @66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4) @83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5) @100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5) • tSAC : 6ns • Default mode by user requirement • MRS cycle with address key programs -. RAS Latency(1 & 2) -. CAS Latency(3 ~ 6) -.

Published: Apr 25, 2005 |