K3S7V2000M-TC Description
Synchronous design allows precise cycle control, with the use of system clock, I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO.
K3S7V2000M-TC Key Features
- JEDEC standard 3.3V power supply
- LVTTL patible with multiplexed address
- All inputs are sampled at the rising edge of the system clock
- tSAC : 6ns
- Default mode by user requirement
- MRS cycle with address key programs -. RAS Latency(1 & 2) -. CAS Latency(3 ~ 6) -. Burst Length : 4, 8 -. Burst Type : S
- DQM for data-out masking
- Package :86TSOP2
K3S7V2000M-TC Applications
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