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KM718V847 - 128Kx36 & 256Kx18 Flow-Through NtRAM

Download the KM718V847 datasheet PDF. This datasheet also covers the KM736V747 variant, as both devices belong to the same 128kx36 & 256kx18 flow-through ntram family and are provided as variant models within a single manufacturer datasheet.

General Description

The KM736V747 and KM718V847 are 4,718,592-bit Synchronous Static SRAMs.

The NtRAMTM, or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles.

Key Features

  • 3.3V+0.165V/-0.165V Power Supply.
  • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • Byte Writable Function.
  • Enable clock and suspend operation.
  • Single READ/WRITE control pin.
  • Self-Timed Write Cycle.
  • Three Chip Enable for simple depth expansion with no data contention.
  • A interleaved burst or a linear burst mode.
  • Asynchronous output enable control.
  • Power Down mode.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (KM736V747_SamsungSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
KM7101 4.9MHz Rail-to-Rail I/O Amplifier Fairchild Semiconductor
KM702 Sensor MEGATRON
KM7660 Voltage Converter Kexin

Other Datasheets by Samsung Semiconductor

Part Number Description
KM718V849 128Kx36 & 256Kx18 Pipelined NtRAM
KM718V887 256Kx18 Synchronous SRAM
KM718V089 512Kx36 & 1Mx18 Synchronous SRAM
KM718V987 256Kx36 & 512Kx18 Synchronous SRAM
KM718FV4021 128Kx36 & 256Kx18 Synchronous Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
KM736V747 KM718V847 Document Title 128Kx36 & 256Kx18 Flow-Through NtRAMTM 128Kx36 & 256Kx18-Bit Flow Through NtRAMTM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed tCD from 8.0ns to 8.5ns at -8 2. Changed tCYC from 13ns to 12ns at -10 3. Changed DC condition at Icc and parameters ISB1 ; from 10mA to 30mA, ISB2 ; from 10mA to 30mA Add VDDQ Supply voltage( 2.5V I/O ) Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O. Final spec Release Remove VDDQ Supply voltage(2.5V I/O) Add VDDQ Supply voltage(2.5V I/O) Change tCD value form 8.5ns to 8.0ns at -8 Draft Date July. 15. 1998 Oct. 10. 1998 Remark Preliminary Preliminary 0.2 0.3 1.0 2.0 3.0 4.0 Dec. 10. 1998 Dec. 23. 1998 Jan. 29. 1999 Feb. 25. 1999 May. 13. 1999 July. 16.