64kx32-bit synchronous pipelined burst sram.
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* Synchronous Operation. 2 Stage Pipelined operation with 4 Burs.
GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each b.
The KM732V696/L is a 2,097,152 bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K words of 32bits and integrates address and control registers, a 2.
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