KM732V696L Datasheet | Samsung Semiconductor

PRELIMINARY KM732V696/L Document Title 64Kx32-Bit Synchronous Pipelined Burst SRAM, 3.3V Power, 2.5V or 3.3V I/O Datasheets for 100TQFP 64Kx32 Synchronous SRAM Revision History Rev . No. Rev. 0.0 Rev. 1.0 History Initial draft Final spec release Draft Date Jan. 19.1996 May. 25. 1997 Remark Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- May 1997 Rev 1.0 PRELIMINARY KM732V696/L 64Kx32 Synchronous SRAM 64Kx32-Bit Synchronous Pipelined Burst SRAM Features - - - - - - - - - - - - - - - - - - Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD=3.3V-5%/+10% Power Supply for 3.3V I/O VDD=3.3V±5% Power Supply for 2.5V I/O I/O Supply Voltage : 3.3V-5%/+10% for 3.3V I/O or 2.5V+0.4V/-0.13V for 2.5V I/O 5V Tolerant Inputs except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. LBO Pin allows a choice of either a interleaved burst or a linear burst. Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 1cycle Disable. Asynchronous Output Enable Control. ADSP, ADSC, ADV Burst Control Pins. TTL-Level Three-State Output....