Mobile-DDR SDRAM
* 1.8V power supply, 1.8V I/O power
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe(DQS)

The default value of the mode register is not defined, therefore the mode register must be written in the power up sequ.

SYMBOL CK, CK TYPE Input DESCRIPTION Mobile-DDR SDRAM Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are .

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