82S117 ram equivalent, 256-bit bipolar ram.
* ORGANIZATION - 256 X 1
* ADDRESS ACCESS TIME - 40n5, MAXIMUM
* WRITE CYCLE TIME - 25n5, MAXIMUM
* POWER DISSIPATION - 1.5mW/BIT TYPICAL
* INPUT LOAD.
such as "Cache", buffers, scratch pads, writable control stores, etc. Both 82S 116 and 82S 117 devices are available in .
The 82S116 and 82S117 are Schottky clamped TTL, read/write memory arrays organ ized as 256 words of one bit each. They feature either open collector or tri-state output options for optimization of word expansion in bussed organ izations. Memory expan.
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