Si53306
feature typical ultra-low jitter characteristics of 50 fs and operate over a wide frequency range. Built-in LDOs deliver high PSRR performance and reduce the need for external ponents, simplifying low-jitter clock distribution in noisy environments.
The Si5330x family is available in multiple configurations, with some versions offering a selectable input clock using a 2:1 input mux. Other features include independent (synchronous) output enable, glitchless switching, LOS monitor of input clocks, output clock division, and built-in format translation. These buffers can be paired with the Si534x clocks and jitter attenuators, the Si5332 clocks, and the Si5xx oscillators to deliver end-to-end clock tree performance.
KEY FEATURES
- Ultra-low additive jitter: 50 fs rms
- Built-in LDOs for high PSRR performance
- Up to 10 outputs
- Any-format Inputs (LVPECL, Low-power
LVPECL, LVDS, CML, HCSL, LVCMOS)
- Wide frequency range
- Output Enable option
- Multiple configuration options
- Dual Bank...
