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TH58NVG7T2ELA46 - 128 GBIT (4G x 8 BIT x 4) CMOS NAND E2PROM

General Description

The TH58NVG7T2E is a single 3.3 V 128 Gbit (145,572,102,144bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 192 pages × 2780 blocks × 4.

Key Features

  • Organization Memory cell array Register Page size Block size TH58NVG7T2E 8568 × 521.3K × 8 x 4 8568 × 8 8568 bytes (1536K + 70.5K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase,Multi Page Copy, Mullti Page Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 10624 blocks Max 11120 blocks.
  • Power supply VCC = 2.7 V to 3.6 V VCCQ = 2.7 V to.

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Datasheet Details

Part number TH58NVG7T2ELA46
Manufacturer Toshiba
File Size 611.09 KB
Description 128 GBIT (4G x 8 BIT x 4) CMOS NAND E2PROM
Datasheet download datasheet TH58NVG7T2ELA46 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TOSHIBA CONFIDENTIAL TH58NVG7T2ELA46 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 128 GBIT (4G × 8 BIT x 4) CMOS NAND E2PROM (Multi-Level-Cell) DESCRIPTION The TH58NVG7T2E is a single 3.3 V 128 Gbit (145,572,102,144bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 192 pages × 2780 blocks × 4. The device has two 8568-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8568-byte increments. The Erase operation is implemented in a single block unit (1536 Kbytes + 70.5 Kbytes:8568 bytes x 192 pages).