U74LVC1G74 Overview
This single positive-edge-triggered D-type flip-flop is designed for 1.65V to 5.5V VCC operation. A low level at the preset(PRE ) or clear ( CLR ) input sets or resets the outputs, regardless of the levels of the other inputs .when PRE and CLR are inactive(high),data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering...
U74LVC1G74 Key Features
- Supports 5V VCC operation
- Inputs accept voltages to 5.5V
- Max tpd of 5.9ns at 3.3V
- Typical VOLP<0.8V at VCC=3.3V, TA=25°C
- Typical VOHV>2V at VCC=3.3V, TA=25°C
- Low Power Consumption, ICC=10μA (Max.)
- Ioff Supports Live Insertion, Partial Power Down Mode, and Back
- ORDERING INFORMATION
- MARKING SOP-8 / MSOP-8