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Vishay Intertechnology Electronic Components Datasheet

SiSS10DN Datasheet

N-Channel 40 V (D-S) MOSFET

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www.vishay.com
SiSS10DN
Vishay Siliconix
N-Channel 40 V (D-S) MOSFET
PRODUCT SUMMARY
VDS (V)
40
RDS(on) () (MAX.)
0.00265 at VGS = 10 V
0.00360 at VGS = 4.5 V
ID (A) a, g
60
60
Qg (TYP.)
23 nC
PowerPAK® 1212-8S
D
D
D
6
7
5
D
8
3.3 mm
1
Top View
3.3 mm
1
4
3
S
2
S
S
G
Bottom View
Ordering Information:
SiSS10DN-T1-GE3 (lead (Pb)-free and halogen-free)
FEATURES
• TrenchFET® Gen IV power MOSFET
• Optimized Qg, Qgd, and Qgd/Qgs ratio
reduces switching related power loss
• 100 % Rg and UIS tested
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Synchronous rectification
• High power density DC/DC
• VRMs and embedded DC/DC
• Synchronous buck converter
• Load switching
• Battery management
D
G
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
ID
TA = 70 °C
Pulsed Drain Current (t = 100 μs)
IDM
Continuous Source-Drain Diode Current
TC = 25 °C
TA = 25 °C
IS
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
L = 0.1 mH
IAS
EAS
TC = 25 °C
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
PD
TA = 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature) d, e
TJ, Tstg
LIMIT
40
+20, -16
60 g
60 g
31.7 b, c
25 b, c
150
51.8
4.3 b, c
30
45
57
36
4.8 b, c
3 b, c
-55 to +150
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient b, f
Maximum Junction-to-Case (Drain)
t 10 s
Steady State
SYMBOL
RthJA
RthJC
TYPICAL
21
1.7
MAXIMUM
26
2.2
UNIT
°C/W
Notes
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8S is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 70 °C/W.
g. Package limited.
S16-0219-Rev. A, 08-Feb-16
1
Document Number: 65439
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000


Vishay Intertechnology Electronic Components Datasheet

SiSS10DN Datasheet

N-Channel 40 V (D-S) MOSFET

No Preview Available !

www.vishay.com
SiSS10DN
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
VDS/TJ
VGS(th)/TJ
ID = 250 μA
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 μA
Gate-Source Leakage
IGSS VDS = 0 V, VGS = +20 V, -16 V
Zero Gate Voltage Drain Current
IDSS
VDS = 40 V, VGS = 0 V
V= 40 V, VDS GS = 0 V, TJ = 55 °C
On-State Drain Current a
ID(on)
VDS 5 V, VGS = 10 V
Drain-Source On-State Resistance a
RDS(on)
VGS = 10 V, ID = 15 A
VGS = 4.5 V, ID = 10 A
Forward Transconductance a
gfs VDS = 10 V, ID = 15 A
Dynamic b
Input Capacitance
Ciss
Output Capacitance
Reverse Transfer Capacitance
Coss
Crss
VDS = 20 V, VGS = 0 V, f = 1 MHz
Crss/Ciss Ratio
Total Gate Charge
Qg V = 20 V, VGS = 10 V, ID = 10 A
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Output Charge
Qoss
Gate Resistance
Rg
Turn-On Delay Time
td(on)
Rise Time
tr
Turn-Off Delay Time
td(off)
Fall Time
tf
Turn-On Delay Time
td(on)
Rise Time
tr
Turn-Off Delay Time
td(off)
Fall Time
tf
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current (t = 100 μs)
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
VDS = 20 V, VGS = 4.5 V, ID = 10 A
VDS = 20 V, VGS = 0 V
f = 1 MHz
VDD = 20 V, RL = 2
ID 10 A, VGEN = 10 V, Rg = 1
VDD = 20 V, RL = 2
ID 10 A, VGEN = 4.5 V, Rg = 1
TC = 25 °C
IS = 5 A
IF = 10 A, dI/dt = 100 A/μs,
TJ = 25 °C
MIN. TYP. MAX. UNIT
40 - - V
- 24 -
mV/°C
- -5.5 -
1.1 - 2.4 V
-
-
± 100
nA
- -1
μA
- - 10
30 - - A
- 0.00220 0.00265
- 0.00300 0.00360
- 70 -
S
- 3750 -
- 560 -
pF
- 72 -
- 0.019 0.038
- 50 75
- 23 35
- 10.3 -
nC
- 4.3 -
- 37 -
0.5 1.2 2.4
- 10 20
- 19 38
- 28 56
- 7 14
ns
- 22 44
- 52 100
- 23 46
- 10 20
- - 51.8
A
- - 150
- 0.73 1.1 V
- 38 76 ns
- 33 66 nC
- 20 -
ns
- 18 -
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S16-0219-Rev. A, 08-Feb-16
2
Document Number: 65439
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000


Part Number SiSS10DN
Description N-Channel 40 V (D-S) MOSFET
Maker Vishay
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