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WCSN0436V1P Datasheet 128kx36 Pipelined Sram

Manufacturer: Weida Semiconductor

Overview: Y7C1350B WCSN0436V1P 128Kx36 Pipelined SRAM with NoBL™ Architecture.

General Description

The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The WCSN0436V1P is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.

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Key Features

  • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736.
  • Supports 166-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Fully registered (inputs and outputs) for pipelined operation www. DataSheet4U. com.
  • Byte Write capability.
  • 128K x 36 common I/O architecture.
  • Single 3.3V power s.

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WCSS0436V1P 256K x 18 Synchronous 3.3V Cache RAM