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WCSS0418V1P - 256K x 18 Synchronous-Pipelined Cache RAM

Datasheet Summary

Description

The WCSS0418V1P is a 3.3V, 256K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

Features

  • Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states.
  • Fully registered inputs and outputs for pipelined operation.
  • 256K by 18 common I/O architecture.
  • 3.3V core power supply.
  • 2.5V / 3.3V I/O operation.
  • Fast clock-to-output times www. DataSheet4U. com.
  • 3.5 ns (for 166-MHz device).
  • 4.0 ns (for 133-MHz device).
  • 5.5 ns (for 100-MHz dev.

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Datasheet preview – WCSS0418V1P

Datasheet Details

Part number WCSS0418V1P
Manufacturer Weida Semiconductor
File Size 707.55 KB
Description 256K x 18 Synchronous-Pipelined Cache RAM
Datasheet download datasheet WCSS0418V1P Datasheet
Additional preview pages of the WCSS0418V1P datasheet.

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Full PDF Text Transcription

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Y7C1327 WCSS0418V1P 256K x 18 Synchronous-Pipelined Cache RAM Features • Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 256K by 18 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times www.DataSheet4U.com — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • • • • • • — 5.5 ns (for 100-MHz device) User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous Output Enable JEDEC-standard 100 TQFP pinout “ZZ” Sleep Mode option and Stop Clock option The WCSS0418V1P I/O pins can operate at either the 2.5V or the 3.
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