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Y7C1350B
WCSN0436V1P
128Kx36 Pipelined SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Fully registered (inputs and outputs) for pipelined operation www.DataSheet4U.com • Byte Write capability • 128K x 36 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 3.8 ns (for 150-MHz device) — 4.0 ns (for 143-MHz device) — 4.2 ns (for 133-MHz device) — 5.0 ns (for 100-MHz device) • • • • • • — 7.
WCSN0436V1P Datasheet
