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WCSS0232V1P - 64K x 32 Synchronous-Pipelined Cache RAM

General Description

The WCSS0232V1P is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

Key Features

  • Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states.
  • Fully registered inputs and outputs for pipelined operation.
  • 64K x 32 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-output times www. DataSheet4U. com All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access de.

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Datasheet Details

Part number WCSS0232V1P
Manufacturer Weida Semiconductor
File Size 415.50 KB
Description 64K x 32 Synchronous-Pipelined Cache RAM
Datasheet download datasheet WCSS0232V1P Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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WCSS0232V1P Revised: February 7, 2002 WCSS0232V1P 64K x 32 Synchronous-Pipelined Cache RAM Features • Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times www.DataSheet4U.com All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns (133-MHz device). The WCSS0232V1P supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC.