datasheet4u.com

900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf





White Electronic
White Electronic

W3E16M64S-XBX Datasheet Preview

W3E16M64S-XBX Datasheet

16Mx64 DDR SDRAM

No Preview Available !

W3E16M64S-XBX pdf
White Electronic Designs
W3E16M64S-XBX
16Mx64 DDR SDRAM
FEATURES
DDR Data Rate = 200, 250, 266Mbps
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
www.DataSheet4U.com
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 64
Weight: W3E16M64S-XBX - 2 grams typical
* This product is subject to change without notice.
BENEFITS
50% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 17% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 64 density
(W3E32M64S-XBX)
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 128MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
February 2005
Rev. 4
Monolithic Solution
11.9 11.9 11.9 11.9
22.3
66
TSOP
TS6O6 PTS6O6 PTS6O6 P TS6O6TPS6O6 P
TST6OS66O6PP
Area
I/O
Count
4 x 265mm2 = 1060mm2
4 x 66 pins = 264 pins
Actual Size
W3E16M64S-XBX
21
White Electronic Designs
W3E16M64S-XBX
25
525mm2
S
A
V
I
N
G
S
50%
219 Balls
17%
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com



White Electronic
White Electronic

W3E16M64S-XBX Datasheet Preview

W3E16M64S-XBX Datasheet

16Mx64 DDR SDRAM

No Preview Available !

W3E16M64S-XBX pdf
White Electronic Designs
W3E16M64S-XBX
FIGURE 1 – PIN CONFIGURATION
Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A DQ13 DQ11 DQ9 VSS VSS A9 A10 A11 A8 VCCQ VCCQ DQ25 DQ27 DQ29 VSS
B DQ15 DQ2 DQ4 DQ6 VSS VSS A0 A7 A6 A1 VCC VCC DQ22 DQ20 DQ18 DQ31
C DQ0 DQ12 DQ10 DQ8 VCC VCC A2 A5 A4 A3 VSS VSS DQ24 DQ26 DQ28 DQ16
D DQ14 DQ3
DQ5
DQ7
VCCQ
VCCQ
A12
DNU
DNU
DNU
VSS
VSS DQ23 DQ21 DQ19 DQ30
E DQ1 DQML0 VCC DQMH0 DQSH3 DQSL0 DQSH0 BA0 BA1 DQSL1 DQSH1 VREF DQML1 VSS
NC DQ17
F CAS0# WE0# VCC CLK0 DQSL3
RAS1# WE1# VSS DQMH1 CLK1
G CS0# RAS0# VCC CKE0 CLK0#
CAS1# CS1# VSS CLK1# CKE1
H VSS VSS VCC VCCQ VSS
VCC VSS VSS VCCQ VCC
J VSS VSS VCC VCCQ VSS
VCC VSS VSS VCCQ VCC
K CLK3# CKE3 VCC CS3# NC
CLK2# CKE2 VSS RAS2# CS2#
L NC CLK3 VCC CAS3# RAS3#
DQSL2# CLK2 VSS WE2# CAS2#
M DQ49 DQMH3 VCC WE3# DQML3 NC NC NC NC NC NC NC DQMH2 VSS DQML2 DQ33
N DQ62 DQ50 DQ52 DQ54 NC NC NC NC NC NC NC DQSH2 DQ39 DQ38 DQ35 DQ46
P DQ48 DQ60 DQ57 DQ56 VSS VSS NC NC NC NC VCC VCC DQ41 DQ42 DQ44 DQ32
R DQ63 DQ51 DQ53 DQ55 VCC VCC NC NC NC NC VSS VSS DQ37 DQ36 DQ34 DQ47
T VSS DQ61 DQ59 DQ58 VCCQ VCCQ
NC
NC
NC
NC
VSS
VSS DQ40 DQ43 DQ45 VCC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
February 2005
Rev. 4
2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


Part Number W3E16M64S-XBX
Description 16Mx64 DDR SDRAM
Maker White Electronic
Total Page 16 Pages
PDF Download
W3E16M64S-XBX pdf
W3E16M64S-XBX Datasheet PDF
[partsNo] view html
View PDF for Mobile








Similar Datasheet

1 W3E16M64S-XBX 16Mx64 DDR SDRAM White Electronic
White Electronic
W3E16M64S-XBX pdf





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy