W3E32M64S-XBX - 32Mx64 DDR SDRAM

Datasheet Summary

Description

The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 536,870,912 bits.

Each chip is internally configured as a quad-bank DRAM.

The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation.

Features

DDR SDRAM rate = 200, 250, 266, 333Mb/s Package:.
219 Plastic Ball Grid Array (PBGA), 25mm x 25mm, 625mm2 W3E32M64S-XBX.

White Electronic

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Datasheet Details

Part number	W3E32M64S-XBX
Manufacturer	White Electronic
File Size	828.27 KB
Description	32Mx64 DDR SDRAM
Datasheet	W3E32M64S-XBX Datasheet
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White Electronic Designs 32Mx64 DDR SDRAM FEATURES DDR SDRAM rate = 200, 250, 266, 333Mb/s Package: • 219 Plastic Ball Grid Array (PBGA), 25mm x 25mm, 625mm2 W3E32M64S-XBX BENEFITS 41% SPACE SAVINGS vs. TSOP Reduced part count Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e.

Published: Jun 8, 2007 |