W3E32M72SR-XSBX - 32Mx72 REGISTERED DDR SDRAM

Datasheet Summary

Description

The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 536,870,912 bits.

Each chip is internally configured as a quad-bank DRAM.

The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation.

Features

Registered for enhanced performance of bus speeds of 200, 250, 266Mb/s Package:.
208 Plastic Ball Grid Array (PBGA), 16 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirecti.

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Datasheet Details

Part number	W3E32M72SR-XSBX
Manufacturer	White Electronic
File Size	743.94 KB
Description	32Mx72 REGISTERED DDR SDRAM
Datasheet	W3E32M72SR-XSBX Datasheet
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White Electronic Designs 32Mx72 REGISTERED DDR SDRAM FEATURES Registered for enhanced performance of bus speeds of 200, 250, 266Mb/s Package: • 208 Plastic Ball Grid Array (PBGA), 16 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e.

Published: Jun 8, 2007 |