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W3E16M64S-XBX - 16Mx64 DDR SDRAM

General Description

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 268,435,456 bits.

Each chip is internally configured as a quad-bank DRAM.

Each of the chip’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.

Key Features

  • DDR Data Rate = 200, 250, 266Mbps Package:.
  • 219 Plastic Ball Grid Array (PBGA), 21 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data capture (one per byte) DQS edge-aligne.

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Datasheet Details

Part number W3E16M64S-XBX
Manufacturer White Electronic
File Size 735.36 KB
Description 16Mx64 DDR SDRAM
Datasheet download datasheet W3E16M64S-XBX Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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White Electronic Designs 16Mx64 DDR SDRAM FEATURES DDR Data Rate = 200, 250, 266Mbps Package: • 219 Plastic Ball Grid Array (PBGA), 21 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CLK www.DataSheet4U.