W3E32M64S-XSBX - 32Mx64 DDR SDRAM

Datasheet Summary

Description

The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 536,870,912 bits.

Each chip is internally configured as a quad-bank DRAM.

The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation.

Features

DDR SDRAM rate = 200, 250, 266, 333.
Package:.
208 Plastic Ball Grid Array (PBGA), 13 x 22mm.
2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) tr.

White Electronic

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Datasheet Details

Part number	W3E32M64S-XSBX
Manufacturer	White Electronic
File Size	749.96 KB
Description	32Mx64 DDR SDRAM
Datasheet	W3E32M64S-XSBX Datasheet
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White Electronic Designs 32Mx64 DDR SDRAM FEATURES DDR SDRAM rate = 200, 250, 266, 333** Package: • 208 Plastic Ball Grid Array (PBGA), 13 x 22mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e.

Published: Jun 8, 2007 |