W3E32M64S-XSBX Datasheet | White Electronic

FEATURES - - DDR SDRAM rate = 200, 250, 266, 333- - Package: - 208 Plastic Ball Grid Array (PBGA), 13 x 22mm - - - - - - - 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 patible) Differential clock inputs (CK and CK#) mands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes mercial, Industrial and Military Temperature Ranges Organized as 32M x 64 - Can be user organized as 2x32Mx32 or 4x32Mx16 - Weight: W3E32M64S-XSBX - 1.5 grams typical - - - - - - BENEFITS - 73% Space Savings vs. FPBGA - 43% Space Savings vs TSOP Reduced part count 21% I/O reduction vs TSOP - 13% I/O reduction vs FPBGA Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match Upgradeable to 64M x 64 density (contact factory for information) GENERAL DESCRIPTION The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide,...