W3E32M72S-XSBX - 32Mx72 DDR SDRAM

Datasheet Summary

Description

The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 536,870,912 bits.

Each chip is internally configured as a quad-bank DRAM.

The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation.

Features

Data rate = 200, 250, 266, 333Mbs Package:.
208 Plastic Ball Grid Array (PBGA), 16 x 22mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ r.

White Electronic

📥 Download Datasheet

Datasheet Details

Part number	W3E32M72S-XSBX
Manufacturer	White Electronic
File Size	491.39 KB
Description	32Mx72 DDR SDRAM
Datasheet	W3E32M72S-XSBX Datasheet
Additional preview pages of the W3E32M72S-XSBX datasheet.

📁 Similar Datasheet

Other Datasheets by White Electronic

W3E32M72S-XBX - 32Mx72 DDR SDRAM
W3E32M72SR-XSBX - 32Mx72 REGISTERED DDR SDRAM
W3E32M64S-XBX - 32Mx64 DDR SDRAM
W3E32M64S-XSBX - 32Mx64 DDR SDRAM
W3E16M64S-XBX - 16Mx64 DDR SDRAM
W3E16M72S-XBX - 16Mx72 Registered DDR SDRAM
W3E16M72SR-XBX - 16Mx72 Registered DDR SDRAM
W3E232M16S-XSTX - 2x32Mx16bit DDR SDRAM

Full PDF Text Transcription

Click to expand full text

White Electronic Designs 32Mx72 DDR SDRAM FEATURES Data rate = 200, 250, 266, 333Mbs Package: • 208 Plastic Ball Grid Array (PBGA), 16 x 22mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e.

Published: Jun 8, 2007 |